EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 137

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Operational Mode Descriptions
Table 5–5. Examples of Shift Operations
Rounding and Saturation Mode
© March 2010 Altera Corporation
Note to
(1) The value of the shift is equal to the value in the bracket where [N] is the position of bit ‘1’ on the B-Input. In the above examples, [N] is 8
Arithmetic Shift Left
Right ASR[32-N]
Logical Shift Right
Rotation ROT[N]
Logical Shift Left
Arithmetic Shift
LSR[32-N]
and is calculated from the LSB to the MSB where LSB=0 and MSB=31.
LSL[N]
ASL[N]
Example
Table
5–5:
Round and saturation functions are often required in DSP arithmetic. Rounding is
used to limit bit growth and its side effects and saturation is used to reduce overflow
and underflow side effects.
Two rounding modes are supported in Stratix III devices:
■
■
You must select one of the two options at compile time.
Round-to-nearest-integer mode provides the biased rounding support and is the
simplest form of rounding commonly used in DSP arithmetic. The round-to-nearest-
even method provides unbiased rounding support and is used where DC offsets are a
concern.
difference between the two modes are listed in
is rounded to 4 bits. You can observe from
the two rounding options is when the residue bits are exactly half way between its
nearest two integers and the LSB is zero (even).
Table 5–6. Example of Round-To-Nearest-Even Mode
Unsigned
Unsigned
Unsigned
Signed
Signed
Signa
Round-to-nearest-integer mode
Round-to-nearest-even mode
6- to 4-bits
Rounding
010111
001101
001010
001110
110111
101101
110110
110010
Table 5–6
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Signb
(Note 1)
lists how round-to-nearest-even mode works. Examples of the
Shift_right
Even (0010)
Even (1100)
Odd (0011)
Odd (1101)
Odd/Even
(Integer)
0
1
0
1
0
x
x
x
x
Rotate
0
0
0
0
1
Fractional
> 0.5 (11)
< 0.5 (01)
= 0.5 (10)
= 0.5 (10)
> 0.5 (11)
< 0.5 (01)
= 0.5 (10)
= 0.5 (10)
Table 5–7
0xAABBCCDD
0xAABBCCDD
0xAABBCCDD
0xAABBCCDD
0xAABBCCDD
A-input
Table
5–7. In this example, a 6-bit input
that the main difference between
Add to Integer
Stratix III Device Handbook, Volume 1
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
B-input
1
0
0
1
1
0
1
0
0xBBCCDD00
0xBBCCDDAA
0xBBCCDD00
0x000000AA
0xFFFFFFAA
Result
0110
0011
0010
0100
1110
1011
1110
1100
Result
5–31