EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 140

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

5–34
DSP Block Control Signals
Table 5–10. DSP Block Dynamic Signals (Part 1 of 2)
Stratix III Device Handbook, Volume 1
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■
output_round
chainout_round
output_saturate
chainout_saturate
accum_sload
zero_chainout
zero_loopback
rotate
shift_right
clock0
clock1
clock2
clock3
signa
signb
Signal Name
—
The Stratix III DSP block is configured using a set of static and dynamic signals. The
DSP block dynamic signals are user configurable and can be set to toggled or not at
run time.
Signed/unsigned control for all multipliers and adders.
signa for “multiplicand” input bus to dataa[17:0] each
multiplier.
signb for “multiplier” input bus datab[17:0] to each multiplier.
signa = 1, signb = 1 for signed-signed multiplication
signa = 1, signb = 0 for signed-unsigned multiplication
signa = 0, signb = 1 for unsigned-signed multiplication
signa = 0, signb = 0 for unsigned-unsigned multiplication
Round control for first stage round/saturation block.
output_round = 1 for rounding on multiply output
output_round = 0 for normal multiply output
Round control for second stage round/saturation block.
chainout_round = 1 for rounding on multiply output
chainout_round = 0 for normal multiply output
Saturation control for first stage round/saturation block for Q-format
multiply. If both rounding and saturation is enabled, saturation is done
on the rounded result.
output_saturate = 1 for saturation support
output_saturate = 0 for no saturation support
Saturation control for second stage round/saturation block for
Q-format multiply. If both rounding and saturation are enabled,
saturation is done on the rounded result.
chainout_saturate = 1 for saturation support
chainout_saturate = 0 for no saturation support
Dynamically specifies whether the accumulator value is zero.
accum_sload = 0, accumulation input is from the output registers
accum_sload = 1, accumulation input is set to be zero
Dynamically specifies whether the chainout value is zero.
Dynamically specifies whether the loopback value is zero.
rotation = 1, rotation feature is enabled
shift_right = 1, shift right feature is enabled
Total Signals per Half-block
DSP-block-wide clock signals
Table 5–10
lists the dynamic signals for the DSP block.
Function
Chapter 5: DSP Blocks in Stratix III Devices
© March 2010 Altera Corporation
Operational Mode Descriptions
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