EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 143

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Application Examples
Figure 5–22. FIR Filter Using Tap-Delay Line Input and Tree Summation of Final Result
© March 2010 Altera Corporation
datab_0[17..0]
datab_1[17..0]
datab_2[17..0]
datab_3[17..0]
datab_4[17..0]
datab_5[17..0]
datab_6[17..0]
datab_7[17..0]
dataa_0[ ]
For faster and more efficient chained cascade summation, the DSP block can
implement the chainout function in the cascade mode. This mode uses the
second-stage 44-bit adder to add the current Four-Multiplier Adder of the half DSP
block to the adjacent half DSP block of the Four-Multiplier Adder as shown in
Figure
This scheme is possible because each half DSP block has two second-stage adders.
One of the two second-stage adders is used to add the current Four-Multiplier Adder.
The second second-stage adder takes the output of the first second-stage adder and
adds it to the adjacent half DSP block of the Four-Multiplier Adder result.
clock[3..0]
5–23.
ena[3..0]
aclr[3..0]
output_saturate
output_round
signa
signb
overflow
Summation
Stratix III Device Handbook, Volume 1
Soft Logic
Adder in
Final
Result
Final
5–37