EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 144

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

5–38
Figure 5–23. FIR Filter using Tap-Delay Line Input and Chained Cascade Summation of Final Result
Stratix III Device Handbook, Volume 1
datab_0[17..0]
datab_1[17..0]
datab_2[17..0]
datab_3[17..0]
datab_4[17..0]
datab_5[17..0]
datab_6[17..0]
datab_7[17..0]
dataa_0[ ]
In
Four-Multiplier Adder is shown as the chainout adder for clarity. This scheme is used
to chain and add multiple DSP blocks together. The output of the chainout adder can
be registered. The registered chainout output can feed the lower adjacent DSP block
for a chainout summation or it can feed general FPGA routing. The chainout result
can be zeroed out by applying logic 1 on the dynamic zerochainout signal. The
zerochainout signal can also be registered.
Delay Register
Figure
clock[3..0]
ena[3..0]
aclr[3..0]
5–23, the adder that adds the adjacent half DSP block to the current
+
+
+
+
chainout_saturate
chainout_round
zero_chainout
signa
signb
+
+
Half-DSP Block
Half-DSP Block
Zero
+
+
chainout_sat_overflow
Chapter 5: DSP Blocks in Stratix III Devices
© March 2010 Altera Corporation
44
result[ ]
Application Examples