EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 147

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Software Support
Figure 5–25. Radix-4 Butterfly
Software Support
© March 2010 Altera Corporation
RAM
RAM
RAM
RAM
A0
A1
A2
A3
f
f
In
multipliers. This can be implemented in Stratix III using three half-DSP blocks
assuming that the data and twiddle wordlengths are 18 bits or fewer.
Altera provides two distinct methods for implementing various modes of the DSP
block in a design: instantiation and inference. Both methods use the following
Quartus II megafunctions:
■
■
■
■
You can instantiate the megafunctions in the Quartus II software to use the DSP block.
Alternatively, with inference, you can create an HDL design and synthesize it using a
third-party synthesis tool (such as LeonardoSpectrum, Synplify, or Quartus II Native
Synthesis) that infers the appropriate megafunction by recognizing multipliers,
multiplier adders, multiplier accumulators, and shift functions. Using either method,
the Quartus II software maps the functionality to the DSP blocks during compilation.
For instructions about using the megafunctions and the MegaWizard Plug-In Manager,
refer to the Quartus II Software Help.
For more information, refer to the
Development Software Handbook.
Figure
LPM_MULT
ALTMULT_ADD
ALTMULT_ACCUM
ALTFP_MULT
X[k,0]
X[k,1]
X[k,2]
X[k,3]
5–25, a radix-4 butterfly is shown. Each butterfly requires three complex
G[k,1]
G[k,2]
G[k,3]
G[k,0]
ROM
Synthesis
0
FFT ENGINE
ROM
1
ROM
section in volume 1 of the Quartus II
2
H[k,0]
H[k,1]
H[k,2]
H[k,3]
BFPU
BFPU
BFPU
BFPU
Stratix III Device Handbook, Volume 1
RAM
RAM
RAM
RAM
A0
A1
A2
A3
5–41