EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 149
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Clock Networks in Stratix III Devices
© July 2010
SIII51006-2.0
Altera Corporation
This chapter describes the hierarchical clock networks and multiple phase-locked
loops (PLLs) with advanced features in Stratix
clocking resources, in combination with the clock synthesis precision provided by the
PLLs, provide a complete clock management solution. The Altera
software compiler automatically turns off clock networks not used in the design,
thereby reducing the overall power consumption of the device.
Stratix III devices deliver abundant PLL resources with up to 12 PLLs per device and
up to 10 outputs per PLL. You can independently program every output, creating a
unique, customizable clock frequency. Inherent jitter filtration and fine granularity
control over multiply, divide ratios, and dynamic phase shift reconfiguration provide
the high performance precision required in today’s high-speed applications. Stratix III
device PLLs are feature-rich, supporting advanced capabilities such as clock
switchover, dynamic phase shifting, PLL reconfiguration, and reconfigurable
bandwidth. Stratix III PLLs also support external feedback mode, spread-spectrum
tracking, and post-scale counter cascading features.
The Quartus II software enables the PLLs and their features without requiring any
external devices. The following sections describe the Stratix III clock networks and
PLLs in detail.
The global clock networks (GCLKs), regional clock networks (RCLKs), and periphery
clock networks (PCLKs) available in Stratix III devices are organized into hierarchical
clock structures that provide up to 220 unique clock domains (16 GCLKs + 88 RCLKs
+ 116 PCLKs) within the Stratix III device and allow up to 67 unique GCLK, RCLK,
and PCLK clock sources (16 GCLKs + 22 RCLKs + 29 PCLKs) per device quadrant.
Table 6–1
Table 6–1. Clock Resources in Stratix III Devices (Part 1 of 2)
Clock input pins
Global clock networks
Regional clock networks
Peripheral clock networks
GCLKs/RCLKs per quadrant
Clock Resource
lists the clock resources available in Stratix III devices.
6. Clock Networks and PLLs in Stratix III
32 Single-ended
(16 Differential)
16
64/88
116 (29 per device quadrant)
(2)
32/38
# of Resources Available
(1)
(3)
®
III devices. The large number of
CLK[0..15]p and
CLK[0..15]n pins
CLK[0..15]p/n pins, PLL
clock outputs, and logic array
CLK[0..15]p/n pins, PLL
clock outputs, and logic array
DPA clock outputs, horizontal
I/O pins, and logic array
16 GCLKs + 16 RCLKs/
16 GCLKs + 22 RCLKs
Stratix III Device Handbook, Volume 1
Source of Clock Resource
®
Quartus
Devices
®
II
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