EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 152

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–4
Figure 6–4. Regional Clock Networks (EP3SL200, EP3SE260, and EP3SL340 Devices)
Note to
(1) The corner RCLKs [64..87] can only be fed by their respective corner PLL outputs. Refer to
Figure 6–5. Periphery Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices)
Stratix III Device Handbook, Volume 1
Figure
6–4:
Periphery Clock Networks
Periphery clock (PCLK) networks shown in
individual clock networks driven from the periphery of the Stratix III device. Clock
outputs from the DPA block, horizontal I/O pins, and internal logic can drive the
PCLK networks. The EP3SL50, EP3SL70, and EP3SE50 devices contain 56 PCLKs; the
EP3SL110, EP3SL150, EP3SL200, EP3SE80, and EP3SE110 devices contain 88 PCLKs;
the EP3SE260 device contains 112 PCLKs, and the EP3SL340 device contains 132
PCLKs. These PCLKs have higher skew compared to GCLK and RCLK networks and
can be used instead of general purpose routing to drive signals into and out of the
Stratix III device.
CLK[0..3]
CLK[0..3]
L1
L2
L3
L4
L2
RCLK[82..87]
RCLK[64..69]
PCLK[14..27]
RCLK[0..5]
RCLK[6..11]
PCLK[0..13]
RCLK[54..63] RCLK[44..53]
RCLK[12..21] RCLK[22..31]
CLK[12..15]
CLK[12..15]
Q1
Q4
CLK[4..7]
Q1
Q4
CLK[4..7]
T1
B1
T1
B1
T2
B2
Q2
Q3
Q2
Q3
RCLK[76..81]
RCLK[32..37]
RCLK[70..75]
RCLK[38..43]
PCLK[28..41]
PCLK[42..55]
Chapter 6: Clock Networks and PLLs in Stratix III Devices
Figure 6–5
Table 6–9 on page 6–13
R1
R2
R3
R4
R2
CLK[8..11]
CLK[8..11]
to
(Note 1)
Figure 6–9
Clock Networks in Stratix III Devices
© July 2010 Altera Corporation
for connectivity.
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