EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 156

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–8
Table 6–2. Clock Input Pin Connectivity to Global Clock Networks
Stratix III Device Handbook, Volume 1
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
Clock Resources
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Logic Array Blocks (LABs)
You can also drive each global and regional clock network via LAB-routing to enable
internal logic to drive a high fan-out, low-skew signal.
Stratix III device PLLs cannot be driven by internally generated GCLKs or RCLKs.
The input clock to the PLL must come from dedicated clock input pins/PLL-fed
GCLKs or RCLKs only.
A spine clock is essentially another layer of routing below global/regional and
periphery clocks before each clock is connected to the clock routing for each LAB row.
The settings for a spine clock are transparent to all users. The Quartus II software
takes care of the spine clock routing based on the global/regional and periphery
clocks.
PLL Clock Outputs
Stratix III PLLs can drive both GCLK and RCLK networks, as detailed in
page 6–12
Table 6–2
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lists the connection between the dedicated clock input pins and GCLKs.
and
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Table 6–9 on page
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6–13.
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CLK (p/n Pins)
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Chapter 6: Clock Networks and PLLs in Stratix III Devices
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Clock Networks in Stratix III Devices
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© July 2010 Altera Corporation
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Table 6–8 on
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