EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 160

EP3SL150F1152C3N

Manufacturer Part Number

EP3SL150F1152C3N

Description

IC STRATX III FPGA 150K 1152FBGA

Manufacturer

Altera

Series

Stratix® IIIr

Datasheets

1.EP3SL150F780C4N.pdf (16 pages)

2.EP3SL150F780C4N.pdf (332 pages)

3.EP3SL150F780C4N.pdf (456 pages)

Specifications of EP3SL150F1152C3N

Number Of Logic Elements/cells

142500

Number Of Labs/clbs

5700

Total Ram Bits

6390

Number Of I /o

744

Voltage - Supply

0.86 V ~ 1.15 V

Mounting Type

Surface Mount

Operating Temperature

0°C ~ 85°C

Package / Case

1152-FBGA

For Use With

544-2568 - KIT DEVELOPMENT STRATIX III

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Number Of Gates

Other names

544-2408
EP3SL150F1152C3NES

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6–12

Table 6–7. Stratix III Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)

Clock Output Connections

Stratix III Device Handbook, Volume 1

CLK13

CLK14

CLK15

PLL_L1_CLKp

PLL_L1_CLKn

PLL_L4_CLKp

PLL_L4_CLKn

PLL_R1_CLKp

PLL_R1_CLKn

PLL_R4_CLKp

PLL_R4_CLKn

Notes to

(1) For compensated PLLs input, only the dedicated CLK pins in the same I/O bank as the PLL used are compensated inputs.

(2) If both PLL_<L1/L4/R1/R4>_CLKp and PLL_<L1/L4/R1/R4>_CLKn pins are not used as a pair of differential clock pins, they can

(3) For single-ended clock input, CLKn pins use the global network to drive the PLLs.

Dedicated Clock Input Pin

be used independently as single-ended clock input pins.

Table

(CLKp/n pins)

6–7:

(2)

(2),(3)

(2)

(2),(3)

(2)

(2),(3)

(2)

(2),(3)

PLLs in Stratix III devices can drive up to 20 regional clock networks and four global

clock networks. Refer to

The Quartus II software automatically assigns PLL clock outputs to regional or global

clock networks.

Table 6–8

Table 6–8. PLL Connectivity to GCLKs on Stratix III Devices (Part 1 of 2)

GCLK0

GCLK1

GCLK2

GCLK3

GCLK4

GCLK5

GCLK6

GCLK7

GCLK8

GCLK9

GCLK10

GCLK11

Clock Network

lists how the PLL clock outputs connect to GCLK networks.

—

Table 6–8

—

for Stratix III PLL connectivity to GCLK networks.

—

PLL Number

Chapter 6: Clock Networks and PLLs in Stratix III Devices

—

(Note 1)

—

PLL Number

—

Clock Networks in Stratix III Devices

—

(Note 1)

—

EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 160

EP3SL150F1152C3N

Specifications of EP3SL150F1152C3N

Available stocks

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