EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 163

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
Clock Networks in Stratix III Devices
© July 2010
Altera Corporation
Figure 6–13
respectively.
Figure 6–13. Stratix III Global Clock Control Block
Notes to
(1) These clock select signals can only be dynamically controlled through internal logic when the device is operating in
(2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
Figure 6–14. Regional Clock Control Block
Notes to
(1) This clock select signal can only be statically controlled through a configuration file (.sof or .pof) and cannot be
(2) CLKn pin is not a dedicated clock input when it is use as a single-ended PLL clock input and it is not fully
The clock source selection for the regional clock select block can only be controlled
statically using configuration bit settings in the configuration file (.sof or .pof)
generated by the Quartus II software.
The Stratix III clock networks can be powered down by both static and dynamic
approaches. When a clock net is powered down, all the logic fed by the clock net is in
an off-state, thereby reducing the overall power consumption of the device. The
unused global and regional clock networks are automatically powered down through
configuration bit settings in the configuration file (.sof or .pof) generated by the
user mode.
controlled during user mode operation.
dynamically controlled during user mode operation.
compensated.
Figure
Figure
and
6–13:
6–14:
Figure 6–14
CLKSELECT[1..0]
PLL Counter
PLL Counter
This multiplexer
supports user-controllable
dynamic switching
Outputs
Outputs
(1)
show the global clock and regional clock select blocks,
2
2
2
CLKp
Pin
Enable/
Disable
RCLK
CLKp
Pins
CLKn
Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
GCLK
CLKn
Internal
Logic
Pin
Static Clock
Select (2)
Internal
Internal
Logic
Logic
Stratix III Device Handbook, Volume 1
6–15