EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 166

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–18
PLLs in Stratix III Devices
Table 6–10. Stratix III Device PLL Availability
Stratix III Device Handbook, Volume 1
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200 (1),
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Notes to
(1) PLLs T2, B2, L3, and R3 are not available in the F780 package.
(2) PLLs L1, L4, R1, and R4 are not available in the H780, F1152, and H1152 packages.
Device
Table
(1)
(1)
(1)
(2)
(1)
(2)
6–10:
(2)
The PLL can remain locked independently of the clkena signals because the
loop-related counters are not affected. This feature is useful for applications that
require a low power or sleep mode. The clkena signal can also disable clock outputs
if the system is not tolerant of frequency overshoot during resynchronization.
Stratix III devices offer up to 12 PLLs that provide robust clock management and
synthesis for device clock management, external system clock management, and
high-speed I/O interfaces. The nomenclature for the PLLs follows their geographical
location in the device floor plan. The PLLs that reside on the top and bottom sides of
the device are named PLL_T1, PLL_T2, PLL_B1 and PLL_B2; the PLLs that reside
on the left and right sides of the device are named PLL_L1, PLL_L2, PLL_L3,
PLL_L4, PLL_R1, PLL_R2, PLL_R3, and PLL_R4, respectively.
Table 6–10
v
v
v
—
—
—
—
—
—
—
L1
v
v
v
v
v
v
v
v
v
v
L2
lists the PLLs available in the Stratix III device family.
v
v
v
v
v
v
v
L3
—
—
—
v
v
v
L4
—
—
—
—
—
—
—
v
v
v
v
v
v
v
v
v
v
T1
v
v
v
v
v
v
v
T2
—
—
—
Chapter 6: Clock Networks and PLLs in Stratix III Devices
B1
v
v
v
v
v
v
v
v
v
v
B2
—
—
v
v
v
v
—
v
v
v
v
v
v
R1
—
—
—
—
—
—
—
© July 2010 Altera Corporation
R2
v
v
v
v
v
v
v
v
v
v
PLLs in Stratix III Devices
R3
—
—
v
v
v
v
—
v
v
v
v
v
v
R4
—
—
—
—
—
—
—