EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 167

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
Table 6–11. Stratix III PLL Features
© July 2010
C (output) counters
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
External feedback input pin
Spread-spectrum input clock tracking
PLL cascading
Compensation modes
PLL drives LVDSCLK and LOADEN
VCO output drives DPA clock
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
Notes to
(1) Provided input clock jitter is within input jitter tolerance specifications.
(2) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
(3) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix III
device can shift all output frequencies in increments of at least 45 degrees. Smaller degree increments are possible depending on the frequency
and divide parameters.
Table
Altera Corporation
6–11:
Feature
All Stratix III PLLs have the same core analog structure with only minor differences in
the features that are supported.
Left/Right PLLs in Stratix III devices.
10
1 to 512
6 single-ended or 4 single-ended and 1
differential pair
4 single-ended or 2 differential pin pairs 4 single-ended or 2 differential pin pairs
Single-ended or differential
Yes
Through GCLK and RCLK and dedicated
path between adjacent PLLs
All except LVDS clock network
compensation
No
No
Down to 96.125 ps
Yes
Yes
Yes
(1)
Stratix III Top/Bottom PLLs
Table 6–11
(3)
lists the features of the Top/Bottom and
7
1 to 512
2 single-ended or 1 differential pair
Single-ended only
Yes
Through GCLK and RCLK and dedicated
path between adjacent PLLs
All except external feedback mode
when using differential I/Os
Yes
Yes
Down to 96.125 ps
Yes
Yes
Yes
(1)
Stratix III Left/Right PLLs
Stratix III Device Handbook, Volume 1
(3)
(2)
6–19