EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 173

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
Table 6–12. PLL Input Signals (Part 2 of 2)
Table 6–13. PLL Output Signals (Part 1 of 2)
© July 2010
areset
pfdena
scanclk
scandata
scanclkena
configupdate
phasecounter
select[3:0]
phaseupdown
phasestep
clk[9..0] for Top/Bottom
PLLs
clk[6..0] for Left/Right
PLLs
clkbad[1..0]
locked
activeclock
scandataout
Port
Altera Corporation
Port
Signal used to reset the PLL which
resynchronizes all the counter outputs.
Active high
Enables the outputs from the phase
frequency detector. Active high
Serial clock signal for the real-time PLL
reconfiguration feature.
Serial input data stream for the real-time
PLL reconfiguration feature.
Enables scanclk and allows the
scandata to be loaded in the scan
chain. Active high
Writes the data in the scan chain to the
PLL. Active high
Selects corresponding PLL counter for
dynamic phase shift
Selects dynamic phase shift direction;
1 = UP; 0 = DOWN
Logic high enables dynamic phase
shifting
Table 6–13
PLL output counters driving
regional, global, or external clocks.
Signals indicating which reference
clock is no longer toggling.
clkbad1 indicates inclk1
status, clkbad0 indicates
inclk0 status. 0 = good; 1 = bad
Lock output from lock detect
circuit. Active high
Signal to indicate which clock
(0 = inclk0 or 1 = inclk1)
is driving the PLL. If this signal is
low, inclk0 drives the PLL. If this
signal is high, inclk1 drives the
PLL.
Output of the last shift register in
the scan chain.
Description
lists the PLL output signals for Stratix III devices.
Description
Logic array or I/O pins
Logic array or I/O pins
Logic array or I/O pin
Logic array or I/O pin
Logic array or I/O pin
PLL switchover circuit
Logic array
Logic array
Logic array
Logic array
PLL clock multiplexer
Source
PLL lock detect
PLL scan chain
PLL counter
Source
Stratix III Device Handbook, Volume 1
General PLL control signal
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
Reconfiguration circuit
Reconfiguration circuit
Internal or external clock
Destination
Destination
Logic array
Logic array
Logic array
Logic array
PFD
6–25