EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 175
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
© July 2010
Altera Corporation
1
Source Synchronous Mode
If the data and clock signals arrive at the same time on the input pins, the same phase
relationship is maintained at the clock and data ports of any IOE input register.
Figure 6–23
mode is recommended for source-synchronous data transfers. Data and clock signals
at the IOE experience similar buffer delays when you use the same I/O standard.
Figure 6–23. Phase Relationship Between Clock and Data in Source-Synchronous Mode
Figure 6–24
Figure 6–24. Phase Relationship Between Clock and Data LVDS Modes
The source-synchronous mode compensates for the delay of the clock network used
plus any difference in the delay between these two paths:
■
■
Set the input pin to register delay chain within the IOE to zero in the Quartus II
software for all data pins clocked by a source-synchronous mode PLL. Also, all data
pins must use the PLL COMPENSATED logic option in the Quartus II software.
Data pin to IOE register input
Clock input pin to the PLL PFD input
shows an example waveform of the clock and data in this mode. This
shows an example waveform of the clock and data in the LVDS mode.
reference clock
Clock at register
reference clock
Clock at register
Data at register
Data at register
at input pin
at input pin
Data pin
Data pin
PLL
PLL
Stratix III Device Handbook, Volume 1
6–27
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