EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 181

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
PLL Control Signals
Clock Switchover
© July 2010
Altera Corporation
1
1
You can use the following three signals to observe and control the PLL operation and
resynchronization.
pfdena
Use the pfdena signal to maintain the most recent locked frequency so your system
has time to store its current settings before shutting down. The pfdena signal
controls the PFD output with a programmable gate. If you disable the PFD, the VCO
is free running and the PLL output drifts. The PLL output jitter may not meet the
datasheet specifications. The lock signal cannot be used as an indicator when the PFD
is disabled.
areset
The areset signal is the reset or resynchronization input for each PLL. The device
input pins or internal logic can drive these input signals. When areset is driven
high, the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock.
The VCO is then set back to its nominal setting. When areset is driven low again,
the PLL will resynchronize to its input as it re-locks.
You should assert the areset signal every time the PLL loses lock to guarantee the
correct phase relationship between the PLL input clock and output clocks. You can set
up the PLL to automatically reset (self reset) upon a loss-of-lock condition using the
Quartus II MegaWizard Plug-In Manager. You should include the areset signal in
designs if the following condition is true:
If the input clock to the PLL is not toggling or is unstable upon power up, assert the
areset signal after the input clock is stable and within specifications.
locked
The lock signal is an asynchronous output of the PLL. The locked output of the PLL
indicates that the PLL has locked onto the reference clock and the PLL clock outputs
are operating at the desired phase and frequency set in the Quartus II MegaWizard
Plug-In Manager. The lock detection circuit provides a signal to the core logic that
gives an indication if the feedback clock has locked onto the reference clock both in
phase and frequency.
Altera recommends that you use the areset and locked signals in your designs to
control and observe the status of your PLL.
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application
such as in a system that turns on the redundant clock if the previous clock stops
running. The design can perform clock switchover automatically, when the clock is no
longer toggling or based on a user control signal, clkswitch.
PLL reconfiguration or clock switchover is enabled in the design.
Stratix III Device Handbook, Volume 1
6–33