EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 186

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–38
Figure 6–36. VCO Switchover Operating Frequency
Stratix III Device Handbook, Volume 1
F vco
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Applications that require a clock switchover feature and a small frequency drift
should use a low-bandwidth PLL. The low-bandwidth PLL reacts more slowly
than a high-bandwidth PLL to reference input clock changes. When the
switchover happens, a low-bandwidth PLL propagates the stopping of the clock to
the output more slowly than a high-bandwidth PLL. However, be aware that the
low-bandwidth PLL also increases lock time.
After a switchover occurs, there may be a finite resynchronization period for the
PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
re-lock depends on the PLL configuration.
The phase relationship between the input clock to the PLL and the output clock
from the PLL is important in your design. Assert areset for at least 10 ns after
performing a clock switchover. Wait for the locked signal to go high and be stable
before re-enabling the output clocks from the PLL.
Figure 6–36
clock is lost and then increases as the VCO locks on to the backup clock.
Disable the system during clock switchover if it is not tolerant of frequency
variations during the PLL resynchronization period. You can use the clkbad[0]
and clkbad[1] status signals to turn off the PFD (PFDENA = 0) so the VCO
maintains its most recent frequency. You can also use the state machine to switch
over to the secondary clock. When the PFD is re-enabled, output clock-enable
signals (clkena) can disable clock outputs during the switchover and
resynchronization period. Once the lock indication is stable, the system can
re-enable the output clocks.
Primary Clock Stops Running
shows how the VCO frequency gradually decreases when the current
Switchover Occurs
Chapter 6: Clock Networks and PLLs in Stratix III Devices
VCO Tracks Secondary Clock
© July 2010 Altera Corporation
PLLs in Stratix III Devices