EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 192

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–44
Table 6–15. Real-Time PLL Reconfiguration Ports
Stratix III Device Handbook, Volume 1
scandata
scanclk
scanclkena
configupdate
scandone
scandataout
PLL Port Name
Table 6–15
(PLD) logic array or I/O pins.
Use the following procedure to reconfigure the PLL counters:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
3. After all 234 bits (Top/Bottom PLLs) or 180 bits (Left/Right PLLs) have been
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
5. The scandone signal goes high indicating the PLL is being reconfigured. A falling
6. Reset the PLL using the areset signal if you make any changes to the M, N, or
7. Steps 1 through 5 can be repeated to reconfigure the PLL any number of times.
the first bit of scandata (Dn).
scanclk.
scanned into the scan chain, the scanclkena signal is de-asserted to prevent
inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
edge indicates the PLL counters have been updated with new settings.
post-scale C counters or the I
Serial input data stream to
scan chain.
Serial clock input signal. This
clock can be free running.
Enables scanclk and
allows the scandata to be
loaded in the scan chain.
Active high
Writes the data in the scan
chain to the PLL. Active high
Indicates when the PLL has
finished reprogramming. A
rising edge indicates the PLL
has begun reprogramming. A
falling edge indicated the
PLL has finished
reprogramming.
Used to output the contents
of the scan chain.
lists how these signals can be driven by the programmable logic device
Description
cp
Logic array or I/O pin
GCLK/RCLK or I/O pins
Logic array or I/O pin
Logic array or I/O pin
PLL reconfiguration circuit
PLL reconfiguration circuit
, R, or C settings.
Chapter 6: Clock Networks and PLLs in Stratix III Devices
Source
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
Logic array or I/O pins
Logic array or I/O pins
© July 2010 Altera Corporation
PLLs in Stratix III Devices
Destination