EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 194
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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6–46
Stratix III Device Handbook, Volume 1
The rselodd bit indicates an odd divide factor for the VCO output frequency along
with a 50% duty cycle. For example, if the post-scale divide factor is 3, the high- and
low-time count values could be set to 2 and 1, respectively, to achieve this division.
This implies a 67%-33% duty cycle. If you need a 50%-50% duty cycle, you can set the
rselodd control bit to 1 to achieve this duty cycle despite an odd division factor. The
PLL implements this duty cycle by transitioning the output clock from high to low on
a falling edge of the VCO output clock. When you set rselodd = 1, you subtract 0.5
cycles from the high time and you add 0.5 cycles to the low time. For example:
■
■
■
Scan Chain Description
The length of the scan chain varies for different Stratix III PLLs. The Top/Bottom
PLLs have 10 post-scale counters and a 234-bit scan chain, while the Left/Right PLLs
have 7 post-scale counters and a 180-bit scan chain.
for each component of a Stratix III PLL.
Table 6–16. Top/Bottom PLL Reprogramming Bits (Part 1 of 2)
C1
C0
N
M
Charge Pump Current
VCO Post-Scale divider (K)
Loop Filter Capacitor
Loop Filter Resistor
Unused CP/LF
C9
C8
C7
C6
C5
C4
C3
C2
High-time count = 2 cycles
Low-time count = 1 cycle
rselodd = 1 effectively equals:
■
■
■
(2)
(3)
High-time count = 1.5 cycles
Low-time count = 1.5 cycles
Duty cycle = (1.5/3) % high-time count and (1.5/3) % low-time count
Block Name
(4)
Counter
16
16
16
16
16
16
16
16
16
16
16
16
0
1
0
0
0
Number of Bits
Chapter 6: Clock Networks and PLLs in Stratix III Devices
Table 6–16
Other
2
2
2
2
2
2
2
2
2
2
2
2
3
0
2
5
7
(1)
© July 2010 Altera Corporation
lists the number of bits
PLLs in Stratix III Devices
Total
18
18
18
18
18
18
18
18
18
18
18
18
3
1
2
5
7
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