EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 198

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–50
Table 6–21. Dynamic Phase-Shifting Control Signals (Part 2 of 2)
Table 6–22. Phase Counter Select Mapping
Stratix III Device Handbook, Volume 1
SCANCLK
PHASEDONE
PHASECOUNTERSELECT[3]
Signal Name
0
0
0
0
0
0
0
0
1
1
1
1
Table 6–22
PHASECOUNTERSELECT setting.
The procedure to perform one dynamic phase-shift step is as follows:
1. Set phaseupdown and phasecounterselect as required.
2. Assert phasestep for at least two scanclk cycles. Each phasestep pulse
3. De-assert phasestep.
4. Wait for phasedone to go high.
5. Repeat steps 1 through 4 as many times as required to perform multiple
All signals are synchronous to scanclk. They are latched on scanclk edges and
must meet t
enables one phase shift.
phase-shifts.
Free running clock from core used
in combination with PHASESTEP
to enable/disable dynamic phase
shifting. Shared with SCANCLK for
dynamic reconfiguration.
When asserted, it indicates to
core-logic that the phase
adjustment is complete and PLL is
ready to act on a possible second
adjustment pulse. Asserts based
on internal PLL timing. De-asserts
on rising edge of SCANCLK.
lists the PLL counter selection based on the corresponding
su
/t
[2]
0
0
0
0
1
1
1
1
0
0
0
0
h
Description
requirements with respect to scanclk edges.
[1]
0
0
1
1
0
0
1
1
0
0
1
1
GCLK/RCLK or I/O pin
PLL reconfiguration circuit
Chapter 6: Clock Networks and PLLs in Stratix III Devices
Source
[0]
0
1
0
1
0
1
0
1
0
1
0
1
© July 2010 Altera Corporation
Logic array or I/O pins
PLL reconfiguration circuit
All Output Counters
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
C5 Counter
C6 Counter
C7 Counter
C8 Counter
C9 Counter
PLLs in Stratix III Devices
M Counter
Selects
Destination