EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 199
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
Figure 6–44. Dynamic Phase Shifting Waveform
© July 2010
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
Altera Corporation
f
Dynamic phase-shifting can be repeated indefinitely. All signals are synchronous to
scanclk and must meet t
The phasestep signal is latched on the negative edge of scanclk. In
this is shown by the second scanclk falling edge. phasestep must stay high for at
least two scanclk cycles. On the second scanclk rising edge after phasestep is
latched (the fourth scanclk rising edge in
and phasecounterselect are latched and the PLL starts dynamic phase-shifting
for the specified counters and in the indicated direction. On the fourth scanclk
rising edge, phasedone goes high to low and remains low until the PLL finishes
dynamic phase-shifting. You can perform another dynamic phase-shift after the
phasedone signal goes from low to high.
Depending on the VCO and scanclk frequencies, phasedone low time (t
may be greater than or less than one scanclk cycle.
After phasedone goes from low to high, you can perform another dynamic phase
shift. Phasestep pulses must be at least one scanclk cycle apart.
For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager,
refer to the
a
ALTPLL_RECONFIG Megafunction User
b
t
CONFIGPHASE
PHASEDONE goes low synchronous with SCANCLK
su
/t
h
requirements with respect to scanclk edges.
c
Figure
d
6–44), the values of phaseupdown
Guide.
Stratix III Device Handbook, Volume 1
Figure
CONFIGPHASE
6–44,
6–51
)
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