EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 205
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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© July 2010 Altera Corporation
SIII51007-1.9
Stratix
while simultaneously providing the high bandwidth required to maximize internal
logic capabilities and produce system-level performance. Independent modular I/O
banks with a common bank structure for vertical migration lend efficiency and
flexibility to the high speed I/O. Package and die enhancements with dynamic
termination and output control provide best-in-class signal integrity. Numerous I/O
features assist in high-speed data transfer into and out of the device, including:
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Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
Low-voltage differential signaling (LVDS), reduced swing differential signal
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and stub series
terminated logic (SSTL)
Single data rate (SDR) and half data rate (HDR—half frequency and twice data
width of SDR) input and output options
Up to 132-full duplex 1.6-Gbps true LVDS channels (132 Tx + 132 Rx) on the row
I/O banks
Hard dynamic phase alignment (DPA) block with serializer/deserializer
(SERDES)
De-skew, read and write leveling, and clock-domain crossing functionality
Programmable output current strength
Programmable slew rate
Programmable delay
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
Serial, parallel, and dynamic on-chip termination (OCT)
Differential OCT
Programmable pre-emphasis
Programmable differential output voltage (V
®
III I/Os are specifically designed for ease of use and rapid system integration
7. Stratix III Device I/O Features
OD
)
Stratix III Device Handbook, Volume 1
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