EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 207

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
Stratix III I/O Standards Support
I/O Standards and Voltage Levels
Table 7–2. I/O Standards and Voltage Levels for Stratix III Devices
© July 2010
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V
LVTTL/LVCMOS
1.8-V
LVTTL/LVCMOS
1.5-V
LVTTL/LVCMOS
1.2-V
LVTTL/LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
I/O Standard
Altera Corporation
PCI-X Rev 1.0
PCI Rev 2.2
JESD8-16A
JESD8-16A
Table 7–1. I/O Standard Applications for Stratix III Devices (Part 2 of 2)
Stratix III devices support a wide range of industry I/O standards, including
single-ended, voltage-referenced single-ended, and differential I/O standards.
Table 7–2
output V
JESD8-11
JESD8-12
JESD8-9B
JESD8-9B
JESD8-15
JESD8-15
Standard
JESD8-B
JESD8-B
JESD8-B
JESD8-B
JESD8-5
JESD8-7
JESD8-6
JESD8-6
JESD8-6
JESD8-6
Support
—
—
CCIO
lists the supported I/O standards and the typical values for input and
, V
Column I/O
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
1.8/1.5
1.8/1.5
CCPD
Banks
I/O Standard
1.2
3.0
3.0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Input Operation
mini-LVDS
LVPECL
, V
REF
, and board V
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
Row I/O
1.8/1.5
1.8/1.5
Banks
1.2
3.0
3.0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
V
CCIO
(V)
Output Operation
Column
Banks
TT
(Note
3.3
3.3
3.0
3.0
2.5
1.8
1.5
1.2
3.0
3.0
2.5
2.5
1.8
1.8
1.5
1.5
1.8
1.8
1.5
1.5
1.2
1.2
.
I/O
1),
Row I/O
(3)
Banks
3.3
3.3
3.0
3.0
2.5
1.8
1.5
1.2
3.0
3.0
2.5
2.5
1.8
1.8
1.5
1.8
1.8
1.5
1.2
—
—
—
Video graphics and clock distribution
(Part 1 of 3)
Voltage)
V
Driver
C CP D
(Pre-
Typical Application
3.3
3.3
3.0
3.0
2.5
2.5
2.5
2.5
3.0
3.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Flat panel display
(V)
Stratix III Device Handbook, Volume 1
Voltage)
V
(Input
1.25
1.25
0.90
0.90
0.75
0.75
0.90
0.90
0.75
0.75
REF
Ref
0.6
0.6
—
—
—
—
—
—
—
—
—
—
(V)
V
Termination
TT
Voltage)
(V) (Board
1.25
1.25
0.90
0.90
0.75
0.75
0.90
0.90
0.75
0.75
0.6
0.6
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—
—
—
—
—
—
—
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