EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 211

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
Stratix III I/O Banks
Modular I/O Banks
© July 2010
Altera Corporation
The I/O pins in Stratix III devices are arranged in groups called modular I/O banks.
Depending on device densities, the number of I/O banks range from 16 to 24 banks.
The size of each bank is 24, 32, 36, 40, or 48 I/O pins.
the number of I/O pins available in each I/O bank and packaging information for
different sets of available devices.
In Stratix III devices, the maximum number of I/O banks per side is four or six,
depending on the device density. When migrating between devices with a different
number of I/O banks per side, it is the middle or “B” bank which is removed or
inserted. For example, when moving from a 24-bank device to a 16-bank device, the
banks that are dropped are “B” banks, namely: 1B, 2B, 3B, 4B, 5B, 6B, 7B, and 8B.
Similarly, when moving from a 16-bank device to a 24-bank device, the banks that are
added are “B” banks, namely: 1B, 2B, 3B, 4B, 5B, 6B, 7B, and 8B.
During migration from a smaller device to a larger device, the bank size increases or
remains the same but never decreases. For example, banks may increase from a size of
24 I/O to a bank of size 32, 36, 40, or 48 I/O, but never decrease.
increase in bank size when migrating from a smaller device to a larger device.
Table 7–3. Bank Migration Path with Increasing Device Size
Note to
(1) Number of I/O shown does not include dedicated clock input pins CLK[1,3,8,10][p,n].
Column I/O
Row I/O
Table
7–3:
Banks
A
B
C
A
B
C
40
24
24
32
24
24
Increase in Bank Size (number of I/O)
(Note 1)
Figure 7–3
Stratix III Device Handbook, Volume 1
48
48
32
48
36
40
to
Table 7–3
Figure 7–5
lists the
—
—
48
—
—
48
show
7–7