EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 217

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
Stratix III I/O Structure
Figure 7–7. IOE Structure for Stratix III Devices
Notes to
(1)
(2) One dynamic OCT control is available per DQ/DQS group.
© July 2010
D3_0 and D3_1
Figure
Firm Core
Altera Corporation
DQS
OE
from
Core
Write
Data
from
Core
clkout
To
Core
To
Core
Read
Data
to
Core
CQn
clkin
f
7–7:
delays have the same available settings in the Quartus
4
4
D4 Delay
2
■
■
■
■
The I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output-enable
(OE) path for handling the OE signal for the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. The input
path consists of the DDR input registers, alignment and synchronization registers,
and HDR. You can bypass each block of the input path.
Figure 7–7
The output and OE paths are divided into output or OE registers, alignment registers,
and HDR blocks. You can bypass each block of the output and OE path.
For more information about I/O registers and how they are used for memory
applications, refer to the
Rate Block
Half Data
Rate Block
Half Data
On-chip series termination without calibration
On-chip parallel termination with calibration (OCT R
On-chip differential termination (OCT R
PCI clamping diode
Rate Block
Half Data
D3_1
Delay
Synchronization
Alignment and
Registers
shows the Stratix III IOE structure.
Alignment
Registers
Alignment
Registers
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
(Note
Q
Q
Q
Q
External Memory Interfaces in Stratix III Devices
1),
D3_0
Delay
Delay
D1
(2)
Input Register
Input Register
®
D
D
PRN
PRN
II software.
D5, D6
Delay
Q
Q
D2 Delay
Programmable
Input Register
Strength and
D
Slew Rate
Current
Control
PRN
D
)
Q
Open Drain
D5, D6
Delay
Output Buffer
Input Buffer
PCI Clamp
DQS Logic Block
T
)
V CCIO
Stratix III Device Handbook, Volume 1
D5_OCT
Dynamic OCT Control (2)
V CCIO
Pull-Up Resistor
Programmable
Termination
Calibration
From OCT
On-Chip
Bus-Hold
Block
D6_OCT
Circuit
chapter.
7–13