EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 219

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
Stratix III I/O Structure
High-Speed Differential I/O with DPA Support
Programmable Current Strength
© July 2010
Altera Corporation
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Table 7–4. Memory Interface Standards Supported (Part 2 of 2)
For more information about external memory interfaces, refer to the
Interfaces in Stratix III Devices
Stratix III devices contain dedicated circuitry for supporting differential standards at
speeds up to 1.6 Gbps. The high-speed differential I/O circuitry supports the
following high speed I/O interconnect standards and applications: Utopia IV, SPI-4.2,
SFI-4, 10 Gigabit Ethernet XSBI, RapidIOTM, and NPSI. Stratix III devices support ×2,
×4, ×6, ×7, ×8, and ×10 SERDES modes for high-speed differential I/O interfaces and
×4, ×6, ×7, ×8, and ×10 SERDES modes with dedicated DPA circuitry. DPA minimizes
bit errors, simplifies PCB layout and timing management for high-speed data transfer,
and eliminates channel-to-channel and channel-to-clock skew in high-speed data
transmission systems.
×2 mode is supported by the DDR registers and is not included in SERDES. For
Stratix III devices, SERDES can be bypassed in the Quartus II MegaWizard
Manager for the ALTLVDS megafunction to support DDR (×2) operation.
Stratix III devices have the following dedicated circuitry for high-speed differential
I/O support:
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■
■
■
■
■
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For more information about DPA support, refer to the
Interfaces with DPA in Stratix III Devices
The output buffer for each Stratix III device I/O pin has a programmable
current-strength control for certain I/O standards. You can use programmable current
strength to mitigate the effects of high signal attenuation due to a long transmission
line or a legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have
several levels of current strength that you can control.
about programmable current strength.
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
Memory Interface Standard
QDR II+ SRAM
DDR3 SDRAM
QDR II SRAM
RLDRAM II
chapter.
chapter.
High-Speed Differential I/O
Table 7–5
Stratix III Device Handbook, Volume 1
I/O Standard
SSTL-15
HSTL-18
HSTL-18
HSTL-15
lists information
External Memory
TM
Plug-In
7–15