EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 231
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 7: Stratix III Device I/O Features
OCT Calibration
OCT Calibration
OCT Calibration Block Location
Figure 7–13. OCT Calibration Block (CB) Location in EP3SL50, EP3SL70, and EP3SE50 Devices
Note to
(1)
© July 2010
Figure 7–13
Figure
Altera Corporation
7–13:
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
CB 1
CB 0
Bank 2A
Bank 1A
Bank 1C
Bank 2C
Stratix III devices support calibrated OCT R
You can calibrate the Stratix III I/O bank with any of eight OCT calibration blocks in
EP3SL50, EP3SL70, EP3SL110, EP3SL150, EP3SE50, EP3SE80, and EP3SE110 devices
and ten OCT calibration blocks in EP3SL200, EP3SE260, and EP3SL340 devices.
Figure
in Stratix III devices.
7–13,
Figure
EP3SE50
EP3SL50
EP3SL70
7–14, and
Figure 7–15
Bank 6A
Bank 6C
Bank 5C
Bank 5A
CB 6
CB 5
show the location of OCT calibration blocks
S
and calibrated OCT R
I/O bank with OCT
calibration block
I/O bank without OCT
calibration block
Stratix III Device Handbook, Volume 1
(Note 1)
T
on all I/O pins.
7–27
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