EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 254

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

8–6
Table 8–2. Number of DQS/DQ Groups in Stratix III Devices per Side (Part 1 of 2)
Stratix III Device Handbook, Volume 1
EP3SE50
EP3SL50
EP3SL70
EP3SE80
EP3SE110
EP3SL110
EP3SL150
EP3SL200
EP3SE260
Device
You must pick your DQS and DQ pins manually for the ×8, ×16/×18, or ×32/×36
DQS/DQ group whose members are being used for RUP and RDN because the
Quartus II software might not be able to place this correctly when there are no specific
pin assignments and might give you a “no-fit” instead.
Table 8–2
device. For a more detailed listing of the number of DQS/DQ groups available per
bank in each Stratix III device, refer to
represent the package bottom view of the Stratix III device.
484-pin FineLine BGA
780-pin FineLine BGA
780-pin FineLine BGA
1152-pin FineLine BGA
780-pin Hybrid FineLine BGA
1152-pin FineLine BGA
1517-pin FineLine BGA
780-pin Hybrid FineLine BGA
1152-pin FineLine BGA
1517-pin FineLine BGA
lists the maximum number of DQS/DQ groups per side of the Stratix III
Package
Left/ Right
Left/ Right
Left/ Right
Left/ Right
Left/ Right
Left/ Right
Left/ Right
Left/ Right
Left/ Right
Left/ Right
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Side
Top/
Top/
Top/
Top/
Top/
Top/
Top/
Top/
Top/
Top/
Figure 8–3
Chapter 8: External Memory Interfaces in Stratix III Devices
×4
12
14
17
14
17
26
26
14
17
26
26
34
38
14
17
26
26
34
38
5
through
(1)
×8/×9
Figure
12
12
12
12
16
18
12
12
16
18
4
2
6
8
6
8
6
8
6
8
© March 2010 Altera Corporation
Memory Interfaces Pin Support
8–7. These figures
×16/×18
0
0
2
2
2
2
4
4
2
2
4
4
6
8
2
2
4
4
6
8
×32/×36
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
4
(2)