EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 257

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Memory Interfaces Pin Support
Figure 8–4. Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, EP3SL70, EP3SE80, EP3SE110, EP3SL110,
EP3SL150, EP3SL200, and EP3SE260 Devices in the 780-pin FineLine BGA Package
Notes to
(1) This device does not support ×32/×36 mode.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as RUP/RDN pins. You cannot use a ×4 group for memory interfaces if two pins of
(3) Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your
(4) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n).
© March 2010 Altera Corporation
the group are being used as RUP and RDN pins for OCT calibration. You can still use the ×16/×18 or ×32/×36 groups that includes these ×4 groups.
However, there are restrictions on using ×8/×9 groups that include these ×4 groups as described on
configuration scheme.
26 User I/Os (4)
26 User I/Os (4)
Figure
I/O Bank 1A (2)
I/O Bank 2A (2)
I/O Bank 1C (3)
32 User I/Os
32 User I/Os
x16/x18=1
I/O Bank 2C
x16/x18=1
x16/x18=0
x16x18=0
x8/x9=2
x8/x9=2
x8/x9=1
x8/x9=1
x4=4
DLL 0
DLL 1
x4=3
x4=4
x4=3
8–4:
I/O Bank 8A (2)
I/O Bank 3A (2)
40 User I/Os
40 User I/Os
x16/x18=1
x16x18=1
EP3SE50, EP3SL50, EP3SL70, EP3SE80, EP3SE110, EP3SL110, EP3SL150,
x8/x9=3
x8/x9=3
x4=6
x4=6
I/O Bank 8C
I/O Bank 3C
24 User I/Os
EP3SL200, and EP3SE260 Devices
x16/x18=0
24 User I/Os
x8/x9=1
x16/x18=0
x8/x9=1
x4=2
x4=2
780-pin FineLine BGA
(2)
(2)
24 User I/Os
I/O Bank 7C
I/O Bank 4C
24 User I/Os
x16/x18=0
x16x18=0
x8/x9=1
x8/x9=1
x4=3
x4=3
I/O Bank 7A (2)
I/O Bank 4A (2)
(Note 1)
40 User I/Os
40 User I/Os
x16/x18=1
x16x18=1
page
x8/x9=3
x8x9=3
x4=6
x4=6
Stratix III Device Handbook, Volume 1
8–5.
26 User I/Os (4)
26 User I/Os (4)
I/O Bank 6A (2)
32 User I/Os
32 User I/Os
I/O Bank 6C
x16/x18=1
I/O Bank 5C
I/O Bank 5A
x16/x18=1
x16/x18=0
x16x18=0
x8/x9=2
x8/x9=1
x8x9=1
x8x9=2
x4=4
x4=3
x4=4
x4=3
DLL 3
DLL 2
(2)
8–9