EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 282

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

8–34
IOE Registers
Stratix III Device Handbook, Volume 1
Figure 8–19. Stratix III Dynamic OCT Control Block
Note to
(1) The write clock comes from either the PLL or the write leveling delay chain.
The IOE registers have been expanded to allow source-synchronous systems to have
faster register-to-register transfers and resynchronization. Both top/bottom and
left/right IOEs have the same capability with left/right IOEs having extra features to
support LVDS data transfer.
Figure 8–20
consists of the DDR input registers, resynchronization registers, and HDR block. You
can bypass each block of the input path.
Figure
8–19:
shows the registers available in the Stratix III input path. The input path
OCT Control Path
OCT Control
OCT Half-
Rate Clock
2
HDR
Block
DFF
Chapter 8: External Memory Interfaces in Stratix III Devices
Write
Clock (1)
Resynchronization
Registers
DFF
OCT Enable
Stratix III External Memory Interface Features
© March 2010 Altera Corporation