EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 283

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Figure 8–20. Stratix III IOE Input Registers
resynchronization Clock
(resync_clk_2x) (5)
clk
CQn (4)
DQS/CQ (3), (9)
DQSn (9)
Differential
Input
Buffer
delayctrlin
(Note 1)
6
DQ
0
1
DDR Input Registers
Input Reg A
Input Reg B
D
D
DFF
DFF
Q
Q
neg_reg_out
I
I
clk
phasectrlin
Input Reg C
I/O Clock Divider (6),(10)
D
4
0111
0110
0101
0100
0011
0010
0001
0000
DFF
phaseinvertctrl
Q
I
0
1
masterin
datain [0]
Alignment & Synchronization Registers
datain [1]
D
D
DFF
DFF
enainputcycledelay
Q
Q
6
D
D
<use_masterin>
DFF
DFF
0
1
enaphasetransferreg
delayctrlin
Q
Q
0
1
0
1
<bypass_output_register>(11)
DFF
D
D
DFF
DFF
Q
Q
0
1
0
1
(2)
phaseselect
D
0
1
D
DFF
DFF
Q
Q
phasectrlin
4
0111
0110
0101
0100
0011
0010
0001
0000
dataout
dataout
phaseinvertctrl
slaveout
clkout
1
0
Half Data Rate Registers
Half-Rate Resynchronization Clock (resync_clk_1x)
D
D
D
D
DFF
DFF
DFF
DFF
Q
Q
Q
Q
D
D
DFF
DFF
Q
Q
dataout [1]
dataout [0]
To Core
To Core
(7)
(7)
to core (7)
directin
To Core dataout [3]
0
1
0
1
dataoutbypass
dataout[2] (7)
(7)
To Core
(8)