EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 285

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Stratix III External Memory Interface Features
© March 2010 Altera Corporation
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock, while the third register aligns the
captured data. You can choose to have the same clock for the positive edge and
negative edge registers, or two different clocks (DQS for positive edge register, and
CQn for negative edge register). The third register that aligns the captured data uses
the same clock as the positive edge registers.
Resynchronization registers consist of up to three levels of registers to resynchronize
the data to the system clock domain. These registers are clocked by the
resynchronization clock that is either generated by the PLL or the read-leveling delay
chain. The outputs of the resynchronization registers can go straight to the core or to
the HDR blocks, which are clocked by the divided-down resynchronization clock.
For more information about the read-leveling delay chain, refer to
Circuitry” on page
Figure 8–21
paths. The path is divided into the HDR block, resynchronization registers, and
output/output-enable registers. The device can bypass each block of the output and
output-enable path.
shows the registers available in the Stratix III output and output-enable
8–31.
Stratix III Device Handbook, Volume 1
“Leveling
8–37