EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 297

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
LVDS Channels
LVDS Channels
Table 9–1. LVDS Channels Supported in Stratix III Device Side I/O Banks
© July 2010
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Notes to
(1) Rx = true LVDS input buffers.
(2) Tx = true LVDS output buffers.
(3) eTx = emulated-LVDS output buffers, either LVDS_E3R or LVDS_E1R.
(4) The EP3SL200 and EP3SL260 FPGAs are offered in the H780 package, instead of the F780 package.
(5) The EP3SL340 FPGA is offered in the H1152 package, instead of the F1152 package.
Device
Table
Altera Corporation
9–1:
1
The Stratix III device supports LVDS on both side I/O banks and column I/O banks.
Single-ended reference clocks are supported when using the source-synchronous
SERDES in DPA and soft-CDR mode. There are true LVDS input and output buffers
on the side I/O banks. On column I/O banks, there are true LVDS input buffers but
do not have true LVDS output buffers. However, you can configure all column user
I/Os—including I/Os with true LVDS input buffers—as emulated LVDS output
buffers. When using emulated LVDS standards, you must implement the logic driving
these pins in soft logic (logic elements) and not hard SERDES.
Emulated differential output buffers support tri-state capability starting with the
Quartus
Table 9–1
484-Pin FineLine
48Rx/eTx +
48Rx/eTx +
48Rx/eTx +
48Tx/eTx
48Tx/eTx
48Tx/eTx
BGA
—
—
—
—
—
—
—
®
II software version 9.1.
lists the LVDS channels supported in Stratix III device side I/O banks.
FineLine BGA
56Tx/eTx
56Tx/eTx
56Rx/eTx +
56Rx/eTx +
56Rx/eTx +
56Rx/eTx +
56Rx/eTx +
56Rx/eTx +
56Rx/eTx +
56Rx/eTx +
56Rx/eTx +
56Tx/eTx
56Tx/eTx
56Tx/eTx
56Tx/eTx
56Tx/eTx
56Tx/eTx
56Tx/eTx
780-Pin
—
(4)
(4)
FineLine BGA
88Tx/eTx
88Rx/eTx +
88Rx/eTx +
88Rx/eTx +
88Rx/eTx +
88Rx/eTx +
88Rx/eTx +
88Rx/eTx +
1152-Pin
88Tx/eTx
88Tx/eTx
88Tx/eTx
88Tx/eTx
88Tx/eTx
88Tx/eTx
—
—
—
(Note
(5)
1), (2),
FineLine BGA
112Rx/eTx +
112Rx/eTx +
112Rx/eTx +
(3)
112Tx/eTx
112Tx/eTx
112Tx/eTx
1517-Pin
Stratix III Device Handbook, Volume 1
—
—
—
—
—
—
—
FineLine BGA
132Rx/eTx +
132Tx/eTx
1780-Pin
—
—
—
—
—
—
—
—
—
9–3