EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 304
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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9–10
Figure 9–9. Soft-CDR Data and Clock Path for a Stratix III Devices
Synchronizer
Stratix III Device Handbook, Volume 1
core
Data to Core
10
f
1
Deserializer
CLK_BS_DES
Figure 9–9
The synchronizer FIFO is bypassed in soft-CDR mode. The reference clock frequency
must be suitable for the PLL to generate a clock that matches the data rate of the
interface. The DPA circuitry can track PPM differences between the reference clock
and the data stream.
The synchronizer is a 1-bit × 6-bit deep FIFO buffer that compensates for the phase
difference between the recovered clock from the DPA circuit and the diffioclk that
clocks the rest of the logic in the receiver. The synchronizer can only compensate for
phase differences, not frequency differences between the data and the receiver’s
INCLK.
An optional port (RX_FIFO_RESET) is available to the internal logic to reset the
synchronizer. Altera
once after the RX_DPA_LOCKED signal gets asserted and before valid data is received.
For more information about how to use the differential receiver, refer to the
Megafunction User
shows the path enabled in soft-CDR mode.
DPA CLK
PCLK
Guide.
®
Bit Slip
recommends using RX_FIFO_RESET to reset the synchronizer
Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Clock Forwarding
Divide Down
ReTimed
Data
and
DPA
LVDS Data
CLOCK
TREE
DPA
© July 2010 Altera Corporation
Differential Receiver
PLL
ALTLVDS
Clock
Ref
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