EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 306

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

9–12
Differential I/O Termination
Left/Right PLLs (PLL_Lx/ PLL_Rx)
Stratix III Device Handbook, Volume 1
f
Stratix III devices provide a 100-Ω OCT R
for LVDS standards. OCT saves board space by eliminating the need to add external
resistors on the board. You can enable OCT in the Quartus II software Assignment
Editor.
OCT R
CLK (0, 2, 9, and 11). It is not supported for column I/O pins, high-speed clock pins
CLK [1, 3, 8, 10], or the corner PLL clock inputs.
Figure 9–11
Figure 9–11. On-Chip Differential I/O Termination for Stratix III Devices
Stratix III devices contain up to eight left/right PLLs, with up to four PLLs located on
the left side and four on the right side of the device. The left PLLs can support
high-speed differential I/O banks on the left side and the right PLLs can support
banks on the right side of the device. The high-speed differential I/O receiver and
transmitter channels use these left/right PLLs to generate the parallel global clocks
(rx- or tx-clock) and high-speed clocks (diffioclk).
of the left/right PLLs. The PLL VCO operates at the clock frequency of the data rate.
Each left/right PLL offers a single serial data rate support, but up to two separate
serialization and/or deserialization factors (from the C0 and C1 left/right PLL clock
outputs). Clock switchover and dynamic left/right PLL reconfiguration is available in
high-speed differential I/O support mode.
For more information, refer to the
D
is supported on all row I/O pins and SERDES block clock pins:
shows the device OCT.
Transmitter
LVDS
Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Clock Network and PLLs in Stratix III Devices
Z
Z
0
0
= 50 Ω
= 50 Ω
D
option on each differential receiver channel
Receiver with On-Chip
Stratix III Differential
100 W Termination
R
D
Figure 9–1
© July 2010 Altera Corporation
shows the locations
Differential I/O Termination
chapter.