EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 307
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Left/Right PLLs (PLL_Lx/ PLL_Rx)
Figure 9–12. PLL Block Diagram for Stratix III Devices
Notes to
(1) n = 6 for Left/Right PLLs; n = 9 for Top/Bottom PLLs.
(2) This is the VCO post-scale counter
(3) The FBOUT port is fed by the M counter in Stratix III PLLs.
(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock
© July 2010
from adjacent PLL
control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally
generated global signal or general purpose I/O pin cannot drive the PLL.
Cascade input
Clock inputs
GCLK/RCLK
Figure
pfdena
from pins
Altera Corporation
(4)
9–12:
4
Figure 9–12
Stratix III PLL.
inclk0
inclk1
Switchover
Clock
Block
K
.
shows a simplified block diagram of the major components of the
÷n
clkswitch
clkbad0
clkbad1
activeclock
PFD
Circuit
Lock
CP
locked
LF
VCO
8
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
÷2
(2)
To DPA block on
Left/Right PLLs
/2, /4
8
8
Stratix III Device Handbook, Volume 1
÷C0
÷C1
÷C2
÷C3
÷Cn
÷m
(1)
Casade output
to adjacent PLL
FBIN
DIFFIOCLK network
GCLK/RCLK network
GCLKs
RCLKs
External clock
outputs
DIFFIOCLK from
Left/Right PLLs
LOAD_EN from
Left/Right PLLs
FBOUT (3)
External
memory
interface DLL
9–13
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