EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 311

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Clocking
Receiver Skew Margin for Non-DPA
© July 2010
Altera Corporation
Table 9–3. Differential Bit Naming (Part 2 of 2)
Changes in system environment, such as temperature, media (cable, connector, or
PCB) loading effect, the receiver’s setup and hold times, and internal skew, reduce the
sampling window for the receiver. The timing margin between the receiver ’s clock
input and the data input sampling window is called receiver skew margin (RSKM).
Figure 9–17
the receiver.
Transmit channel-to-channel skew (TCCS), RSKM, and the sampling window
specifications are used for high-speed source-synchronous differential signals without
DPA. When using DPA, these specifications are exchanged for the simpler single DPA
jitter tolerance specification. For instance, the receiver skew is why each input with
DPA selects a different phase of the clock, thus removing the requirement for this
margin. In the timing diagram, TSW represents time for the sampling window.
Receiver Channel Data
Number
shows the relationship between the RSKM and the sampling window of
17
18
MSB Position
135
143
Internal 8-Bit Parallel Data
Stratix III Device Handbook, Volume 1
LSB Position
128
136
9–17