EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 326

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

10–2
I/O Pins Remain Tri-Stated During Power Up
Insertion or Removal of a Stratix III Device from a Powered-Up System
Hot-Socketing Feature Implementation in Stratix III Devices
Stratix III Device Handbook, Volume 1
f
A device that does not support hot socketing can interrupt system operation or cause
contention by driving out before or during power up. In a hot-socketing situation, the
Stratix III device's output buffers are turned off during system power up or power
down. Also, the Stratix III device does not drive out until the device is configured and
working within recommended operating conditions.
Devices that do not support hot socketing can short power supplies when powered
up through the device signal pins. This irregular power up can damage both the
driving and driven devices and can disrupt card power up.
You can insert a Stratix III device into or remove it from a powered-up system board
without damaging the system board or interfering with its operation.
You can power up or power down the core voltage supplies (V
and V
time between them. The individual power supply ramp-up and ramp-down rates can
range from 50 μs to 12 ms or 100 ms depending on the PORSEL setting. During hot
socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is
less than 20 pF.
For more information about the hot socketing specification, refer to the
Switching Characteristics of Stratix III Devices
Power-Sequencing Feature and Testing for Altera Devices White
A possible concern regarding hot socketing is the potential for “latch-up”.
Nevertheless, Stratix III devices are immune to latch-up when hot socketing. Latch-up
can occur when electrical subsystems are hot socketed into an active system. During
hot socketing, the signal pins can be connected and driven by the active system before
the power supply can provide current to the device's power and ground planes. This
condition can lead to latch-up and cause a low-impedance path from power to ground
within the device. As a result, the device draws a large amount of current, possibly
causing electrical damage.
The hot-socketing feature turns off the output buffer during power up and power
down of the V
generates an internal HOTSCKT signal when the V
supplies are below the threshold voltage. Hot-socketing circuitry is designed to
prevent excess I/O leakage during power up. When the voltage ramps up very
slowly, it is still relatively low, even after the POR signal is released and the
configuration is completed. The CONF_DONE, nCEO, and nSTATUS pins fail to
respond, as the output buffer cannot flip from the state set by the hot-socketing circuit
at this low voltage. Therefore, the hot-socketing circuit has been removed on these
configuration pins to make sure that they are able to operate during configuration.
Thus, it is expected behavior for these pins to drive out during power-up and
power-down sequences.
CCD_PLL
), V
CC
CCIO
, V
, V
CCIO
CCPMG
, V
CCPGM
, V
CC_CLKIN
, or V
Chapter 10: Hot Socketing and Power-On Reset in Stratix III Devices
CCPD
, and V
power supplies. The hot-socketing circuitry
CCPD
Hot-Socketing Feature Implementation in Stratix III Devices
chapter and the
supplies in any sequence and at any
CC
, V
CCIO
, V
Paper.
Hot-Socketing and
CCPGM
© March 2010 Altera Corporation
CC
, V
, or V
CCL
, V
CCPD
DC and
CCPT
power
, V
CCA_PLL
,