EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 327
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 10: Hot Socketing and Power-On Reset in Stratix III Devices
Hot-Socketing Feature Implementation in Stratix III Devices
© March 2010
Altera Corporation
1
Figure 10–1
Figure 10–1. Hot-Socketing Circuitry for Stratix III Devices
The POR circuit monitors the voltage level of power supplies (V
and V
pull-up resistor (R) in the Stratix III input/output element (IOE) keeps the I/O pins
from floating. The 3.3-V tolerance control circuit permits the I/O pins to be driven by
3.3 V before V
I/O pins from driving out when the device is not in user mode.
Altera uses GND as reference for hot-socketing operation and I/O buffer designs. To
ensure proper operation, you must connect the GND between boards before
connecting the power supplies. This will prevent the GND on your board from being
pulled up inadvertently by a path to power through other components on your board.
A pulled up GND could otherwise cause an out-of-specification I/O voltage or
current condition with the Altera device.
CCPT
) and keeps the I/O pins tri-stated until the device is in user mode. The weak
shows the Stratix III device’s I/O pin circuitry.
Resistor
Pull-Up
Weak
CCIO
PAD
, V
CC
, V
R
CCPD
, and/or V
V
CCIO
CCPGM
supplies are powered, and it prevents the
Tolerance
to Logic Array
Voltage
Control
Input Buffer
Output Enable
Stratix III Device Handbook, Volume 1
Pre-Driver
Hot Socket
Output
CC
Power On
Monitor
Reset
, V
CCL
, V
CCPD
, V
CCPGM
10–3
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