EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 333

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Configuration Devices
Configuration Schemes
© March 2011 Altera Corporation
SIII51011-2.0
f
1
This chapter contains complete information about Stratix
schemes, how to execute the required configuration schemes, and all necessary option
pin settings.
Stratix III devices use SRAM cells to store configuration data. Because SRAM memory
is volatile, you must download configuration data to the Stratix III device each time
the device powers up. You can configure Stratix III devices using one of four
configuration schemes:
■
■
■
■
All configuration schemes use an external controller (for example, a MAX
or microprocessor), a configuration device, or a download cable. Refer to
“Configuration Features” on page 11–3
The Altera
single-device and multi-device configuration solution for Stratix III devices and are
used in the fast AS configuration scheme. Serial configuration devices offer a
low-cost, low-pin count configuration solution.
For information about serial configuration devices, refer to the
Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Configuration Handbook.
All minimum timing information in this handbook covers the entire Stratix III family.
Some devices may work at less than the minimum timing stated in this handbook due
to process variation.
Select the configuration scheme by driving the Stratix III device MSEL pins either high
or low, as detailed in
supply of the bank they reside in. The MSEL[2..0] pins have 5-kΩ internal
pull-down resistors that are always active. During power-on reset (POR) and
reconfiguration, the MSEL pins must be at LVTTL V
logic low and logic high.
To avoid any problems with detecting an incorrect configuration scheme, hard-wire
the MSEL[] pins to V
not drive the MSEL[] pins with a microprocessor or another device.
Fast passive parallel (FPP)
Fast active serial (AS)
Passive serial (PS)
Joint Test Action Group (JTAG)
®
serial configuration devices (EPCS128, EPCS64, and EPCS16) support a
Table
CCPGM
and GND, without any pull-up or pull-down resistors. Do
11–1. The MSEL pins are powered by the V
11. Configuring Stratix III Devices
for more information.
IL
and V
®
III supported configuration
Stratix III Device Handbook, Volume 1
IH
levels to be considered a
Serial Configuration
in volume 2 of the
CCPGM
®
power
II device