EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 334

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–2
Stratix III Device Handbook, Volume 1
f
Table 11–1. Stratix III Configuration Schemes
Table 11–2
Stratix III devices.
Table 11–2. Stratix III Uncompressed Raw Binary File (.rbf) Sizes
Use the data in
configuration file formats, such as a hexadecimal (.hex) or tabular text file (.ttf)
format, have different file sizes. Refer to the Quartus
types of configuration file and the file sizes. However, for any specific version of the
Quartus II software, any design targeted for the same device will have the same
uncompressed configuration file size. If you are using compression, the file size can
vary after each compilation because the compression ratio is dependent on the design.
For more information about setting device configuration options or creating
configuration files, refer to the
Formats
Fast passive parallel (FPP)
Passive serial (PS)
Fast AS (40 MHz)
Remote system upgrade fast AS (40 MHz)
(1)
FPP with design security feature,
decompression, or both enabled
JTAG-based configuration
Notes to
(1) To support fast AS configuration for Stratix III, you must use EPCS16, EPCS64, or EPCS128 devices. For more
(2) These modes are only supported when using a MAX
(3) Do not leave the MSEL pins floating. Connect them to VCCPGM or ground. These pins support the non-JTAG
(4) JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
information, refer to
configuration. In these modes, the host system must output a DCLK that is ×4 the data rate.
configuration scheme used in production. If you only use JTAG configuration, connect the MSEL pins to ground.
are ignored.
Device
Table
chapters in volume 2 of the Configuration Handbook.
Configuration Scheme
lists the uncompressed raw binary file (.rbf) configuration file sizes for
11–1:
Table 11–2
(1)
Serial Configuration Devices Data Sheet
(4)
to estimate the file size before design compilation. Different
(2)
Device Configuration Options
Data Size (Bits)
117, 387, 664
22, 178, 792
22, 178, 792
47, 413, 312
47, 413, 312
93, 324, 656
25, 891, 968
48, 225, 392
48, 225, 392
93, 324, 656
®
MSEL2
II device or a microprocessor with flash memory for
(3)
0
0
0
0
0
chapter.
®
Chapter 11: Configuring Stratix III Devices
II software for the different
MSEL1
and
(3)
© March 2011 Altera Corporation
0
1
1
1
0
Configuration File
Configuration Devices
MSEL0
(3)
0
0
1
1
1