EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 340

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–8
Fast Passive Parallel Configuration
FPP Configuration Using a MAX II Device as an External Host
Stratix III Device Handbook, Volume 1
1
Fast passive parallel (FPP) configuration in Stratix III devices is designed to meet the
continuously increasing demand for faster configuration times. Stratix III devices are
designed with the capability of receiving byte-wide configuration data per clock
cycle.
Table 11–4. Stratix III MSEL Pin Settings for FPP Configuration Schemes
You can perform FPP configuration of Stratix III devices using an intelligent host,
such as a MAX II device, or a microprocessor.
FPP configuration using compression and an external host provides the fastest
method to configure Stratix III devices. In this configuration scheme, you can use a
MAX II device as an intelligent host that controls the transfer of configuration data
from a storage device, such as flash memory, to the target Stratix III device. You can
store configuration data in .rbf, .hex, or .ttf format. When using the MAX II device as
an intelligent host, a design that controls the configuration process, such as fetching
the data from flash memory and sending it to the device, must be stored in the MAX II
device.
If you are using the Stratix III decompression feature, design security feature or both,
the external host must be able to send a DCLK frequency that is four times the data
rate.
The ×4 DCLK signal does not require an additional pin and is sent on the DCLK pin.
The maximum DCLK frequency is 100 MHz, which results in a maximum data rate of
200 Mbps. If you are not using the Stratix III decompression or design security
features, the data rate is the same as the DCLK frequency.
Fast Passive Parallel (FPP)
FPP with the design security feature, decompression feature, or
both enabled
Note to
(1) These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is ×4 the data rate.
Table 11–4
Table
11–4:
(1)
lists the MSEL pin settings when using the FPP configuration scheme.
Configuration Scheme
Chapter 11: Configuring Stratix III Devices
MSEL2
© March 2011 Altera Corporation
Fast Passive Parallel Configuration
0
0
MSEL1
0
0
MSEL0
0
1