EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 341

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
© March 2011 Altera Corporation
1
1
Figure 11–3
device and a MAX II device for single device configuration.
Figure 11–3. Single Device FPP Configuration Using an External Host
Note to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix III device. V
Upon power-up, the Stratix III device goes through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is
approximately 100 ms. When PORSEL is driven high, the POR time is approximately
12 ms. During POR, the device resets, holds nSTATUS low, and tri-states all user I/O
pins. After the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are on (after
POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS is low, the device is in the reset stage. To initiate
configuration, the MAX II device must drive the nCONFIG pin from low to high.
V
reside must be fully powered to the appropriate voltage levels to begin the
configuration process.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the MAX II device places
the configuration data one byte at a time on the DATA[7..0] pins.
Stratix III devices receive configuration data on the DATA[7..0] pins and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If
you are using the Stratix III decompression feature, design security feature, or both,
the configuration data is latched on the rising edge of every fourth DCLK cycle. After
the configuration data is latched in, it is processed during the following three DCLK
cycles.
CC
, V
high enough to meet the V
configuration system’s I/O with V
Figure
CCIO
, V
11–3:
shows the configuration interface connections between the Stratix III
CCPGM
(MAX II Device or
Microprocessor)
External Host
ADDR DATA[7..0]
, and V
Memory
IH
specification of the I/O on the external host. It is recommended to power up all
CCPD
CCPGM
of the banks where the configuration and JTAG pins
.
10 kΩ
V
CCPGM
(1)
V
CCPGM
10 kΩ
GND
(1)
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix III Device
Stratix III Device Handbook, Volume 1
MSEL[2..0]
nCEO
GND
N.C.
CCPGM
should be
11–9