EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 342

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–10
Stratix III Device Handbook, Volume 1
1
Data is continuously clocked into the target device until CONF_DONE goes high. A
low-to-high transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin. The CONF_DONE pin must have an external
10-kΩ pull-up resistor for the device to initialize.
In Stratix III devices, the initialization clock source is either the internal oscillator
(typically 10 MHz) or the optional CLKUSR pin. By default, the internal oscillator is
the clock source for initialization. If you use the internal oscillator, the Stratix III
device receives enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to the device
after configuration is complete does not affect device operation.
You can also synchronize initialization of multiple devices or delay initialization with
the CLKUSR option. You can turn on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software from the General tab of the Device and
Pin Options dialog box. Supplying a clock on CLKUSR does not affect the
configuration process. After the CONF_DONE pin transitions high, CLKUSR is enabled
after the time specified as t
require 4,436 clock cycles to initialize properly and enter user mode. Stratix III devices
support a CLKUSR f
An optional INIT_DONE pin is available, which signals the end of initialization and
the start of user mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software on the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high because of an
external 10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high. The
MAX II device must be able to detect this low-to-high transition, which signals the
device has entered user mode. When initialization is complete, the device enters user
mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. During configuration, DATA[7..0] pins are powered by V
entering user mode, these pins are available as user I/O pins that are powered by
V
I/O pins are tri-stated in user mode. To change this default option in the Quartus II
software, select the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified frequency to
ensure correct configuration. No maximum DCLK period exists, which means you can
pause configuration by halting DCLK for an indefinite amount of time.
If you are using the Stratix III decompression feature, design security feature, or both
and need to stop DCLK, it can only be stopped three clock cycles after the last data byte
was latched into the Stratix III device. If you are using the Stratix III device without
decompression or design security feature, the DCLK can only be stopped two clock
cycles after the last data byte was latched into the Stratix III device.
CCIO
. When you select the FPP scheme as a default in the Quartus II software, these
MAX
of 100 MHz.
CD2CU
. When this time period elapses, Stratix III devices
Chapter 11: Configuring Stratix III Devices
© March 2011 Altera Corporation
Fast Passive Parallel Configuration
CCPGM
. After