EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 343

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
© March 2011 Altera Corporation
1
1
By stopping DCLK, the configuration circuit allows enough clock cycles to process the
last byte of latched configuration data. When the clock restarts, the MAX II device
must provide data on the DATA[7..0] pins prior to sending the first DCLK rising
edge.
If an error occurs during configuration, the device drives its nSTATUS pin low,
resetting itself internally. The low signal on the nSTATUS pin also alerts the MAX II
device that there is an error. If the Auto-restart configuration after error option
(available in the Quartus II software on the General tab of the Device and Pin
Options dialog box) is turned on, the device releases nSTATUS after a reset time-out
period (maximum of 100 μs). After nSTATUS is released and pulled high by a pull-up
resistor, the MAX II device can try to reconfigure the target device without needing to
pulse nCONFIG low. If this option is turned off, the MAX II device must generate a
low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG to restart the
configuration process.
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
The MAX II device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The MAX II device must monitor the CONF_DONE pin to
detect errors and determine when programming completes. If all configuration data is
sent, but the CONF_DONE or INIT_DONE signals have not gone high, the MAX II
device will reconfigure the target device.
If you use the optional CLKUSR pin and the nCONFIG is pulled low to restart
configuration during device initialization, you must ensure CLKUSR continues
toggling during the time nSTATUS is low (maximum of 100 µs).
When the device is in user mode, transitioning the nCONFIG pin low to high initiates
a reconfiguration. The nCONFIG pin should be low for at least 2 μs. When nCONFIG is
pulled low, the device also pulls nSTATUS and CONF_DONE low and all I/O pins are
tri-stated. After nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
Stratix III Device Handbook, Volume 1
STATUS
specification.
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