EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 347

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
Table 11–5. FPP Timing Parameters for Stratix III Devices
Figure 11–7. FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled
Notes to
(1) Use this timing waveform when the decompression feature, design security feature, or both are used.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(3) Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.
(4) Upon power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. Drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings.
(7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to sending
(8) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
© March 2011 Altera Corporation
t
f
t
t
t
t
t
Notes to
(1) Use these timing parameters when the decompression and design security features are not used.
(2) This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting up the device.
CLK
M AX
R
CD2UM
CD2C U
CD2UM C
Symbol
When nCONFIG is pulled low, a reconfiguration cycle begins.
the first DCLK rising edge.
(4)
(3)
CONF_DONE
Figure
DATA[7..0]
INIT_DONE
Table
nSTATUS
nCONFIG
User I/O
DCLK
DCLK period
DCLK frequency
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
11–7:
11–5:
t
t
CF2CD
CFG
t
Figure 11–7
device as an external host. This waveform shows the timing when the decompression
feature, design security feature, or both are enabled.
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
1
2
Byte 0
t
DH
shows the timing waveform for FPP configuration when using a MAX II
3
Parameter
4
(3)
1
t
CH
2
Byte 1
t
CLK
t
t
CL
DH
3
(Note 1)
4
(7)
(7)
(Part 2 of 2)
Byte 2
1
tCD2CU + (4,436
4 × maximum
DCLK period
Byte ( n -1)
× CLKUSR
3
Minimum
period)
10
—
—
—
20
4
(8)
Stratix III Device Handbook, Volume 1
Byte n
t
CD2UM
Maximum
(5)
(6)
100
100
—
40
40
—
—
(Note
User Mode
User Mode
1),
Units
MHz
(2)
ns
ns
ns
μs
—
—
11–15