EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 348

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–16
Table 11–6. FPP Timing Parameters for Stratix III Devices with Decompression or Design Security Feature Enabled
FPP Configuration Using a Microprocessor
Stratix III Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
Notes to
(1) Use these timing parameters when the decompression and design security features are used.
(2) This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting up the device.
(Note 1)
CF 2CD
CF 2ST0
CF G
STATUS
CF 2ST1
CF 2CK
ST2C K
DSU
DH
CH
CL
CLK
M AX
DATA
R
CD2UM
CD2C U
CD2UM C
Symbol
Table
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
Data rate
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
f
11–6:
1
Table 11–6
when the decompression feature, design security feature, or both are enabled.
Device configuration options and how to create configuration files are discussed
further in the
volume 2 of the Configuration Handbook.
In this configuration scheme, a microprocessor can control the transfer of
configuration data from a storage device, such as flash memory, to the target Stratix III
device.
All information in
on page 11–8
to this section for all configuration and timing information.
defines the timing parameters for Stratix III devices for FPP configuration
is also applicable when using a microprocessor as an external host. Refer
Device Configuration
Parameter
“FPP Configuration Using a MAX II Device as an External Host”
(3)
Options and
Configuration File Formats
CLKUSR period)
t
CD2C U
4 × maximum
DCLK period
Minimum
Chapter 11: Configuring Stratix III Devices
+ (4,436 ×
100
—
—
10
—
30
10
—
—
—
—
20
2
2
5
4
4
© March 2011 Altera Corporation
Fast Passive Parallel Configuration
Maximum
100
100
800
800
100
200
100
—
—
—
—
—
40
40
—
—
—
—
—
chapters in
(2)
(2)
Mbps
Units
MHz
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs