EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 350

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–18
Stratix III Device Handbook, Volume 1
1
Figure 11–8. Single Device Fast AS Configuration
Notes to
(1) Connect the pull-up resistors to V
(2) Stratix III devices use the ASDO-to-ASDI path to control the configuration device.
Upon power-up, the Stratix III devices go through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is
approximately 100 ms. If PORSEL is driven high, the POR time is approximately
12 ms. During POR, the device will reset, hold nSTATUS and CONF_DONE low, and
tri-state all user I/O pins. After the device successfully exits POR, all user I/O pins
continue to be tri-stated. If nIO_pullup is driven low during power-up and
configuration, the user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If nIO_pullup is
driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS are low, the device is in reset. After POR, the Stratix III
device releases nSTATUS, which is pulled high by an external 10-kΩ pull-up resistor
and enters configuration mode.
To begin configuration, power the V
where the configuration and JTAG pins reside) to the appropriate voltage levels.
The serial clock (DCLK) generated by the Stratix III device controls the entire
configuration cycle and provides the timing for the serial interface. Stratix III devices
use an internal oscillator to generate DCLK. Using the MSEL[] pins, you can select to
use a 40 MHz oscillator.
In fast AS configuration schemes, Stratix III devices drive out control signals on the
falling edge of DCLK. The serial configuration device responds to the instructions by
driving out configuration data on the falling edge of DCLK. Then the data is latched
into the Stratix III device on the following falling edge of DCLK.
Figure
Serial Configuration
11–8:
Device
DATA
DCLK
ASDI
nCS
V
CCPGM
CCPGM
10 kΩ
(1)
at 3.3-V supply.
V
CCPGM
CC
(2)
, V
10 kΩ
(1)
CCIO
Fast Active Serial Configuration (Serial Configuration Devices)
V
GND
CCPGM
, V
10 kΩ
CCPGM
(1)
nCONFIG
nSTATUS
CONF_DONE
nCE
DATA0
DCLK
nCSO
ASDO
, and V
Stratix III FPGA
Chapter 11: Configuring Stratix III Devices
CCPD
© March 2011 Altera Corporation
MSEL2
MSEL1
MSEL0
nCEO
voltages (for the banks
V
CCPGM
N.C.
GND