EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 354
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
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490
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11–22
Stratix III Device Handbook, Volume 1
If the configuration bitstream size exceeds the capacity of a serial configuration
device, you must select a larger configuration device, enable the compression feature,
or both. When configuring multiple devices, the size of the bitstream is the sum of the
individual devices’ configuration bitstreams.
A system may have multiple devices that contain the same configuration data. In
active serial chains, you can implement this by storing one copy of the SOF in the
serial configuration device. The same copy of the SOF configures the master Stratix III
device and all remaining slave devices concurrently. All Stratix III devices must be the
same density and package. The master device is set up in active serial mode and the
slave devices are set up in passive serial mode.
To configure four identical Stratix III devices with the same SOF, you could set up the
chain similar to the example shown in
device, and its MSEL pins should be set to select AS configuration. The other three
slave devices are set up for concurrent configuration, and their MSEL pins should be
set to select PS configuration. The nCE input pins from the master and slave are
connected to GND, and the DATA and DCLK pins connect in parallel to all four devices.
During the configuration cycle, the master device reads its configuration data from
the serial configuration device and transmits the second copy of the configuration
data to all three slave devices, configuring all of them simultaneously.
Figure
Fast Active Serial Configuration (Serial Configuration Devices)
11–10. The first device is the master
Chapter 11: Configuring Stratix III Devices
© March 2011 Altera Corporation
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