EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 355

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
Figure 11–10. Multi-Device Fast AS Configuration When the Devices Receive the Same Data Using a Single SOF
Notes to
(1) Connect the pull-up resistors to V
(2) Connect the repeater buffers between the Stratix III master and slave device(s) for DATA[0] and DCLK. This prevents any potential signal
Estimating Active Serial Configuration Time
© March 2011 Altera Corporation
integrity and clock skew problems.
Figure
Serial Configuration
11–10:
Device
DATA
DCLK
ASDI
nCS
Active serial configuration time is dominated by the time it takes to transfer data from
the serial configuration device to the Stratix III device. This serial interface is clocked
by the Stratix III DCLK output (generated from an internal oscillator). Because the
Stratix III device only supports fast AS configuration, the DCLK frequency needs to be
set to 40 MHz (25 ns). The minimum configuration time estimate for an EP3SL50
device (15 MBits of uncompressed data) is shown in
Equation 11–1.
Example 11–1.
RBF Size × (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum configuration
V CCPGM (1)
10 kΩ
CCPGM
V CCPGM (1)
Buffers (2)
10 kΩ
at 3.3-V supply.
V CCPGM (1)
GND
10 kΩ
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
FPGA Master
Stratix III
15 Mbits × (25 ns / 1 bit) = 375 ms
MSEL2
MSEL1
MSEL0
nCEO
V
CCPGM
N.C.
GND
GND
time
Equation 11–1
nSTATUS
CONF_DONE
nCONFIG
nCE
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
DATA0
DCLK
FPGA Slave
FPGA Slave
FPGA Slave
Stratix III Device Handbook, Volume 1
Stratix III
Stratix III
Stratix III
MSEL2
MSEL1
MSEL0
MSEL2
MSEL1
MSEL0
MSEL2
MSEL1
MSEL0
nCEO
nCEO
nCEO
and
GND
GND
GND
Example
N.C.
N.C.
N.C.
V
V
V
CCPGM
CCPGM
CCPGM
11–1.
11–23