EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 356

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–24
Figure 11–11. Fast AS Configuration Timing
Stratix III Device Handbook, Volume 1
CONF_DONE
INIT_DONE
nSTATUS
nCONFIG
User I/O
DATA0
ASDO
nCSO
DCLK
t
POR
Enabling compression reduces the amount of configuration data that is transmitted to
the Stratix III device, which also reduces configuration time. On average, compression
reduces configuration time, depending on the design.
Figure 11–11
Table 11–8
configuration.
Table 11–8. Fast AS Timing Parameters for Stratix III Devices
f
t
t
t
t
t
t
CLK
CF 2ST1
DSU
DH
CH
CL
CD2UM
Symbol
Read Address
defines the timing parameters for Stratix III devices for fast AS
DCLK frequency from Stratix III
nCONFIG high to nSTATUS high
Data setup time before falling edge on DCLK
Data hold time after falling edge on DCLK
DCLK high time
DCLK low time
CONF_DONE high to user mode
shows the timing waveform for AS configuration.
t
DSU
t
DH
bit N
bit N - 1
Parameter
t
CH
bit 1
t
CL
Fast Active Serial Configuration (Serial Configuration Devices)
bit 0
Chapter 11: Configuring Stratix III Devices
© March 2011 Altera Corporation
t
CD2UM
Min
15
—
10
10
20
7
0
Typ
25
—
—
—
—
—
—
User Mode
Max Units
100
100
40
—
—
—
—
MHz
μs
ns
ns
ns
ns
μs